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IS61NW6432
IS61NW6432
64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
FEATURES
Fast access time: 5 ns-100 MHz; 6 ns-83 MHz; 7 ns-75 MHz; 8ns-66 MHz; No wait cycles between Read and write Internal self-timed write cycle Individual byte write Control Clock controlled, registered address, data and control PentiumTM or Inear burst sequence control using MODE input Three chip enables for simple depth depth expansion and adress pipelining Common data inputs and data outputs JEDEC 100-pin LQFP and PQFP package Single+3.3V power supply Optional data strobe pin (#80) for latching data (See page 12 for detailed timing)
DESCRIPTION
The IS61NW6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, no-wait bus, secondary cache for the Pentium, 680X0, and Power PC microprocessors. It is organized as 65,536 words by 32 bits, fabricated with ICSI's advanced CMOS technology. Incorporating a no-wait bus, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a Positive-edge-trggered clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CEN is HIGH. In this state the internal device will hold their previous values. When the ADV/LD is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV/LD is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when RD/WE is LOW. Separate byte enables allow indiviual bytes to be written. BW1 controls I/O1-I/P8; BW2 controls I/O9-I/O16;BW3 controls I/ O17-I/O24; BW4 controls I/O25-I/O32. All Bytes are written when BW1, BW2, BW3, and BW4 are LOW. MODE pin upon power up is in interleave burst mode. It can be connected to GND or VccQ to alter power up state.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SSR006-0B
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IS61NW6432
BLOCK DIAGRAM
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Integrated Circuit Solution Inc.
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IS61NW6432
PIN CONFIGURATION
100-Pin LQFP and PQFP (Top View)
A6 A7 CE1 CE2 BW4 BW3 BW2 BW1 CE3 VCC GND CLK R/W CEN OE ADV/LD NC NC A8 A9
NC I/O17 I/O18 VCCQ GNDQ I/O19 I/O20 I/O21 I/O22 GNDQ VCCQ I/O23 I/O24 VCC VCC VCC GND I/O25 I/O26 VCCQ GNDQ I/O27 I/O28 I/O29 I/O30 GNDQ VCCQ I/O31 I/O32 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 NC
NC I/O16 I/O15 VCCQ GNDQ I/O14 I/O13 I/O12 I/O11 GNDQ VCCQ I/O10 I/O9 GND VCC VCC GND I/O8 I/O7 VCCQ GNDQ I/O6 I/O5 I/O4 I/O3 GNDQ VCCQ I/O2 I/O1 NC
PIN DESCRIPTIONS
A0-A15 CLK CEN ADV/CD BW1-BW4 R/W CE1, CE2, CE3 OE DS
Notes: 1. Optional, NC or DS.
Address Inputs Clock Clock Enale Advance Load Synchronous Byte Write Enable Read / Write Synchronous Chip Enable Output Enable Data Strobe
I/O-I/O32 MODE VCC GND VCCQ GNDQ NC
Data Input/Output Burst Sequence Mode +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Isolated Output Buffer Ground No Connect
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IS61NW6432
TRUTH TABLE(1)
Operation Bein New Write Cycle Begin New Read Cycle Advance Burst Counter (Burst Write) Advance Burst Counter (BurstRead) Deselect (2 Cycle) Hold/NOOP
"
Address Used External External Internal Internal X X
R/W /W L H X X X X
CEx L L X X H X
ADV/LD /LD L L H H L X
CEN L L L L L H
BWx BW Valid X Valid X X X
CLK L-H L-H L-H L-H L-H L-H
Notes: 1. "X" Means don't care. 2. When ADV/LD signal is sampled HI|GH, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced, Therefore, the nature of the burst cycle (Read or Write) is deternined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when CEx is sampled HIGH and ADV/LD sampled LOW at rising edge of clock. The data bus will tristate two cycles after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked form propogating through the part. The state of all the internal registers remains unchanged.
PARTIAL TRUTH TABLE(Non-burst)
Function READ WRITE Byte 1 WRITE Byte 2 WRITE Byte 3 WRITE Byte 4 WRITE All Bytes GW H L L L L L BW1 X L H H H L BW2 BW3 X H L H H L X H H L H L BW4 X H H H L L CEx L L L L L X ADV/LD /LD L L L L L L
FUNCTIONAL TIMING DIAGRAM
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IS61NW6432
TYPICAL OPERATION CE1, CE3 and CEN are LOW, CE2 is HIGH, Non-Burst Operation
Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n+15 n+16 n+17 n+18 n+19 n+20 n+21 Address A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 R/W H L H L H L H L H L H H L L H H H L L L H H ADV/LD L L L L L L L L L L L L L L L L L L L L L L CEX L L L L L L L L L L L L L L L L L L L L L L CEN L L L L L L L L L L L L L L L L L L L L L L BWX X L X L X L X L X L X X L L X X X L L L X X OE ? ? L X L X L X L X L X L L X X L L L x X X I/O D-2 D-1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 Comments ? ? Data Out Data In Data Out Data In Data Out Data In Data Out Data In Data Out Data In Data Out Data Out Data In Data In Data Out Data Out Data Out Data In Data In Data In
Notes: 1. H=High; L=Low; X=Don't Care;?=Don't Know; Z=High lmpedance
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IS61NW6432
READ OPERATION
Cycle Address R/W n n+1 n+2 A0 X X H X X ADV/LD LD L X X CEX L L X CEN X L X BWX X X X OE X X L I/O X X D0 Comments Address and Control meet setup Clock Setup valid Contents of Address A0 Read Out
BURST READ OPERATION
Cycle Address R/W n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 A0 X X X X A1 X X A2 H X X X X H X X H ADV/LD LD L H H H H L H H L CEX L X X X X L X X L CEN X L L L L L L L L BWX X X X X X X X X X OE X X L L L L L L L I/O X X D0 D0+1 D0+2 D0+3 D0 D1 D0+1 Comments Address and Control meet setup Clock Setup valid, Advance Counter Address A0 Read Out, Inc. Count Address A0+1 Read Out, Inc. Count Address A0+2 Read Out, Inc. Count Address A0+3 Read Out, Load A1 Address A0 Read Out, Inc. Count Address A1 Read Out, Inc. Count Address A0+1 Read Out, Load A2
WRITE OPERATION
Cycle Address R/W n n+1 n+2 A0 X X L X X ADV/LD LD L X X CEX L L X CEN L L L BWX L X X OE X X X I/O X X D0 Comments Address and Control meet setup Clock Setup valid Write D0 to Address A0
BURST WRITE OPERATION
Cycle Address R/W n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 A0 X X X X A1 X X A2 H X X H X L X X L ADV/LD LD L H H H H L H H L CEX L X X L X L X X L CEN L L L L L L L L L BWX L L L X L L L L L OE X X X L X X X X X I/O X X D0 D0+1 D0+2 D0+3 D0 D1 D0+1 Comments Address and Control meet setup Clock Setup valid, Inc. Count Address A0 Write Out, Inc. Count Address A0+1 Write Out, Inc. Count Address A0+2 Write Out, Inc. Count Address A0+3 Write Out, Load A1 Address A0 Write Out, Inc. Count Address A1 Write Out, Inc. Count Address A0+1 Write Out, Load A2
Notes: 1. H=High; L=Low; X=Don't Care;?=Don't Know; Z=High lmpedance
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IS61NW6432
READ OPERATION WITH CLOCK ENABLE USED
Cycle Address R/W n n+1 n+2 n+3 n+4 n+5 n+6 n+7 A0 X A1 X X A2 A3 A4 H X H X X H ? ? ADV/LD LD L X L X X L L L CEX L X L X X L L L CEN L H L H H L L L BWX X X X X X X X X OE X X X L L L L L I/O X X X D0 D0 D0 D1 D2 Comments Address and Control meet setup Clock n+1 lgnored Clock Valid Clock lgnored, Data D0 is on the bus Clock lgnored, Data D0 is on the bus Address A0 Read Out (bus trans.) Address A1 Read Out (bus trans.) Address A2 Read Out (bus trans.)
READ OPERATION WITH CLOCK ENABLE USED
Cycle Address R/W n n+1 n+2 n+3 n+4 n+5 n+6 n+7 A0 X A1 X X A2 A3 A4 L X L X X L ? ? ADV/LD LD L X L X X L L L CEX L X L X X L L L CEN L H L H H L L L BWX L X L X X L L L OE X X X L L L L L I/O X X X di di D0 D1 D2 Comments Address and Control meet setup Clock n+1 lgnored Clock Valid Clock lgnored. Clock lgnored. Write data D0 (bus trans.) Write data D1 (bus trans.) Write data D2 (bus trans.)
Notes: 1. H=High; L=Low; X=Don't Care;?=Don't Know; Z=High lmpedance
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IS61NW6432
INTERLEAVED BURST ADDRESS TABLE (MODE=V++3 or No connect)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Addres A1 A0 11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE=GND3)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Value 10 to +85 55 to +150 1.8 100 0.5 to VCCQ + 0.3 0.5 to 5.5 Unit C C W mA V V
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
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Integrated Circuit Solution Inc.
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IS61NW6432
OPERATING RANGE
Range Commercial Ambient Temperature 0C to +70C VCC 3.3V +10%, 5%
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND < VIN < VCCQ
Test Conditions IOH = 5.0 mA IOL = 5.0 mA
Min. 2.4 1.7 0.3 Com. Com. 5 5
Max. 0.4 VCCQ + 0.3 0.8 5 5
Unit V V V V A A
GND < VOUT < VCCQ, OE = VIH
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol Parameter ICC AC Operating Supply Current Standby Current Test Conditions -5 Min.Typ. Max. -6 -7 Min.Typ.Max. Min.Typ.Max. 220 210 -8 Min.Typ.Max. 200 Unit mA
Device Selected, Com. 230 All Inputs = VIL or VIH OE = VIH,Cycle Time > tKC min. Device Deselected, Com. VCC = Max., All Inputs= VIH or VIL CLK Cycle Time > tKC min. CEN=VIH 60
ISB
60
60
60
mA
Note: 1. MODE pin has an internal pull up. This pin may be a No Connect, tied to GND, or tied to VCCQ. 2. MODE pin should be tied to Vcc or GND. It exhibit 30 A maximum leakage current when tied to < GND + 0.2V or > Vcc 0. 2V.
Integrated Circuit Solution Inc.
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IS61NW6432
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1
AC TEST LOADS
317 3.3V
ZO = 50
OUTPUT
Output Buffer
30 pF
50
5 pF Including jig and scope
351
1.5V
Figure 1
Figure 2
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Integrated Circuit Solution Inc.
SSR006-0B
IS61NW6432
READ /WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol fmax tKC tKH tKL tKQ tKQX
Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Address Hold Time Clock EnableHold Time Write Hold Time Chip Enable Hold Time
Min. 10 4 4 1.5 2.0 1.5 0 0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5
-5
Max. 100 5 3.5 5 3.5
Min. 12 4 4 1.5 2.0 2 0 0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 0.5 2.0 0.5 1.5
-6
Max. 83 6 3.5 6 3.5 2.5
Min. 13 6 6 1.5 2.0 2 0 0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 0.5 2.0 0.5 1.5
-7
Max 75 7 3.5 6 3.5 2.5
-8 Min. 15 6 6 1.5 2.0 2 0 0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 0.5 2.0 0.5 1.5
Max. 66 8 3.5 6 3.5 2.5
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKQLZ tKQHZ tOEQ tOEQX
tOELZ tOEHZ tAS tWS tCES tSE tAVS tAE tHE tWH tCEH tALS tALH tds tdh tzp
Advance/Load (ADV/LD) Setup Time2.0 Advance/Load (ADV/LD) Hold Time 0.5 Data Setup Time Data Hold Time I/O From Tri-State to Valid 2.0 0.5 1.5
Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled.
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IS61NW6432
READ/WRITE CYCLE TIMING
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Integrated Circuit Solution Inc.
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IS61NW6432
ORDERING INFORMATION Commercial Range: 0C to +70C
Frequency (MHz) 5 6 7 8 Order Part Number Package IS61NW6432-5TQ 14*20*1.4mm LQFP IS61NW6432-5PQ 14*20*2.7mm PQFP IS61NW6432-6TQ 14*20*1.4mm LQFP IS61NW6432-6PQ 14*20*2.7mm PQFP IS61NW6432-7TQ 14*20*1.4mm LQFP IS61NW6432-7PQ 14*20*2.7mm PQFP IS61NW6432-8TQ 14*20*1.4mm LQFP IS61NW6432-8PQ 14*20*2.7mm PQFP
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000
Integrated Circuit Solution Inc.
BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
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IS61NW6432
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